1. Field of the Invention
The present invention generally relates to an impedance tuning apparatus.
2. Description of Related Art
Referring to FIG. 1, a circuit diagram of a conventional impedance tuning apparatus 100 is shown. In the impedance tuning apparatus 100, a tuned resistor Rdut and a reference resistor Rref are serially connected with each other, and are respectively coupled to current sources IS1 and IS2. Voltage drops generated by currents flowing through the tuned resistor Rdut and the reference resistor Rref via the current sources IS1 and IS2 are simultaneously transmitted to comparators CMP1 and CMP2 to be respectively compared with reference voltages VC1 and VC2. A controller 110 generates a tuning signal TUN according to comparison results DN and UP of the comparators CMP1 and CMP2, so as to tune a resistance value of the tuned resistor Rdut. The reference voltages VC1 and VC2 are respectively generated by a current provided by a current source IS3 flowing through reference resistors ΔR and RA1.
In the impedance tuning apparatus 100 in FIG. 1, both the comparators CMP1 and CMP2 are constructed by using an operation amplifier. However, the comparison results of the comparators CMP1 and CMP2 are distorted because of the property of input voltage offset of the operation amplifier. In addition, errors of the reference resistors ΔR and RA1 for generating the reference voltages VC1 and VC2 also affect the accuracy of the comparison results of the comparators CMP1 and CMP2. The errors generated by the above factors will be more serious, especially when the impedance tuning apparatus 100 is in the form of an Integrated Circuit (IC), and an impedance tuning result of the tuned resistor Rdut is greatly degraded.